The present application relates to multilevel power inverters, and more particularly to medium-voltage and line-voltage three-level power inverters.
Note that the points discussed below may reflect the hindsight gained from the disclosed inventions, and are not necessarily admitted to be prior art. In particular, note that the following discussion also recapitulates many teachings found in the parent applications.
Parent application US 2014-0375287 (which is hereby incorporated by reference) disclosed a fully bidirectional bipolar transistor with two base terminals. Such transistors are referred to as “B-TRANs.” The base region of the transistor is preferably the bulk of a semiconductor die. The transistor preferably has two emitter/collector regions, one on each face of the die. Two distinct base contact regions are also provided—one on each face of the die. Thus, for example, with a p-type semiconductor die, each face would include an n+ emitter/collector region and a p-type base contact region. Isolation trenches and peripheral field-limiting rings are preferably also included, but in essence the B-TRAN is a four-terminal three-layer device.
An example of a B-TRAN structure is generally illustrated in FIG. 4. In this Figure, both faces of a semiconductor die carry emitter/collector regions which form a junction with the bulk substrate. Base contact regions are also present on both faces. This example shows an npn structure, so the emitter/collector regions are n-type, and the base contact regions are p-type. A shallow n+ contact doping provides ohmic contact from the separate emitter/collector terminals (on the two opposite faces of the semiconductor die, in this example) to the emitter/collector regions, and a shallow p+ contact doping provides ohmic contact from the separate base terminals (on the two opposite faces of the die) to the base contact regions. In this example, the dielectric-filled trenches provide lateral separation between the base contact regions and the emitter/collector regions. However, each trench can also include a conducting region, such as doped polysilicon, that is surrounded by a dielectric, and is electrically connected to the emitter/collector to form a vertical field plate, increasing breakdown voltage. (Note that a p-type diffused region may be added to reduce the series resistance between the emitter-to-base junction and the base contact.) B-TRANs can provide significantly better efficiency than is conventionally available for existing static transfer switches; for example, a 1200V B-TRAN has an expected system efficiency of 99.9%.
Parent application US 2014-0375287 also describes some surprising aspects of operation of this kind of device. Notably: 1) when the device is turned on, it is preferably first operated merely as a diode, and base drive is then applied to reduce the on-state voltage drop. 2) Base drive is preferably applied to the base nearest whichever emitter/collector region will be acting as the collector (as determined by the external voltage seen at the device terminals). This operation is very different from typical bipolar transistor operation, where the base contact is (typically) closely connected to the emitter-base junction but may be far from the collector contact. 3) A two-stage turnoff sequence is preferably used. In the first stage of turnoff, the transistor is brought out of full bipolar conduction, but still is connected to operate as a diode; in the final state of turnoff diode conduction is blocked too. 4) In the off state, base-emitter voltage (on each side) is limited by an external low-voltage diode which parallels that base-emitter junction. This prevents either of the base-emitter junctions from getting anywhere close to forward bias, and avoids the degradation of breakdown voltage which can occur otherwise.
Since the B-TRAN is a fully symmetric device, there is no difference between the two emitter/collector regions. However, in describing the operation of the device, the externally applied voltage will determine which side is (instantaneously) acting as the emitter, and which is acting as the collector. The two base contact terminals are accordingly referred as the “e-base” and “c-base”, where the c-base terminal is on the side of the device which happens to be the collector side at a given moment.
FIG. 3A shows a sample equivalent circuit for one exemplary NPN B-TRAN. Body diodes 312A and 312B can correspond to e.g. the upper and lower P-N junctions, respectively. Switches 314A and 314B can short respective base terminals 108A and 108B to respective emitter/collector terminals 106A and 106B.
In one sample embodiment, a B-TRAN can have six phases of operation in each direction, as follows.
1) Initially, as seen in FIG. 3B, voltage on emitter/collector terminal T1 is positive with respect to emitter/collector terminal T2. Switches 314A and 316A are open, leaving base terminal B1 open. Switch 314B is closed, shorting base terminal B2 to emitter/collector terminal T2. This, in turn, functionally bypasses body diode 312B. In this state, the device is turned off. No current will flow in this state, due to the reverse-biased P-N junction (represented by body diode 312A) at the upper side of the device.
2) As seen in FIG. 3C, the voltage on emitter/collector terminal T1 is brought negative with respect to emitter/collector terminal T2. P-N diode junction 312A is now forward biased, and now begins injecting electrons into the drift region. Current flows as for a forward-biased diode.
After a short time, e.g. a few microseconds, the drift layer is well-charged. The forward voltage drop is low, but greater in magnitude than 0.7 V (a typical silicon diode voltage drop). In one sample embodiment, a typical forward voltage drop (Vf) at a typical current density of e.g. 200 A/cm2 can have a magnitude of e.g. 1.0 V.
3) To further reduce forward voltage drop Vf, the conductivity of the drift region is increased, as in e.g. FIG. 3D. To inject more charge carriers (here, holes) into the drift region, thereby increasing its conductivity and decreasing forward voltage drop Vf, base terminal B2 is disconnected from terminal T2 by opening switch 314B. Base terminal B2 is then connected to a source of positive charge by switch 316B. In one sample embodiment, the source of positive charge can be, e.g., a capacitor charged to +1.5 VDC. As a result, a surge current will flow into the drift region, thus injecting holes. This will in turn cause upper P-N diode junction 312A to inject even more electrons into the drift region. This significantly increases the conductivity of the drift region and decreases forward voltage drop Vf to e.g. 0.1-0.2 V, placing the device into saturation.
4) Continuing in the sample embodiment of FIG. 3D, current continuously flows into the drift region through base terminal B2 to maintain a low forward voltage drop Vf. The necessary current magnitude is determined by, e.g., the gain of equivalent NPN transistor 318. As the device is being driven in a high level injection regime, this gain is determined by high level recombination factors such as e.g. surface recombination velocity, rather than by low-level-regime factors such as thickness of, and carrier lifetime within, the base/drift region.
5) To turn the device off, as in e.g. FIG. 3E, base terminal B2 is disconnected from the positive power supply and connected instead to emitter terminal T2, opening switch 316B and closing switch 314B. This causes a large current to flow out of the drift region, which in turn rapidly takes the device out of saturation. Closing switch 314A connects base terminal B1 to collector terminal T1, stopping electron injection at upper P-N junction 312A. Both of these actions rapidly remove charge carriers from the drift region while only slightly increasing forward voltage drop Vf. As both base terminals are shorted to the respective emitter/collector terminals by switches 314A and 314B, body diodes 312A and 312B are both functionally bypassed.
6) Finally, at an optimum time (which can be e.g. nominally 2 μs for a 1200 V device), full turn-off can occur, as seen in e.g. FIG. 3F. Full turn-off can begin by opening switch 314B, disconnecting base terminal B2 from corresponding terminal T2. This causes a depletion region to form from lower P-N diode junction 312B as it goes into reverse bias. Any remaining charge carriers recombine, or are collected at the upper base. The device stops conducting and blocks forward voltage.
The procedure of steps 1-6 can, when modified appropriately, used to operate the device in the opposite direction. Steps 1-6 can also be modified to operate a PNP B-TRAN (e.g. by inverting all relevant polarities).
Note that, even though the B-TRAN is a four-terminal device, with two base contact regions which are operated separately, its device physics are those of a three-layer device—i.e. it only has one base region. That is the center of the die's vertical extent, between the two emitter junctions. Since the B-TRAN is a symmetrically bipolar device, only one of the two emitter/collector regions will be operating as an emitter at any given moment; but the bottom junction of either emitter/collector region is referred to here, for convenience, as an “emitter junction.”
A somewhat similar structure was shown and described in application WO2014/122472 of Wood. However, that application is primarily directed to different structures. The Wood application also does not describe the methods of operation described in the US 2014-0375287 application.
“Inverter” is the general term for a circuit which converts DC to AC. In power electronics, inverters are often used to convert DC power from batteries or solar banks for use. A typical power inverter device or circuit requires a relatively stable DC power source capable of supplying enough current for the intended power demands of the system. The input voltage depends on the design and purpose of the inverter. Examples include:                12 VDC, for smaller consumer and commercial inverters that typically run from a rechargeable 12 V lead acid battery.        24 and 48 VDC, which are common standards for home energy systems.        200 to 400 VDC, when power is from photovoltaic solar panels.        300 to 450 VDC, when power is from electric vehicle battery packs in vehicle-to-grid systems.        Hundreds of thousands of volts, where the inverter is part of a high voltage direct current power transmission system.        
One particular type of power inverter is the three level inverter, where each output line can be connected to one of three voltage levels. (When the power source is a two-voltage DC supply, a “neutral” voltage leg can be generated by capacitors, as shown in FIG. 2A.) Three level inverters offer several advantages over the more common two level inverter. As compared to two level inverters, three level inverters have smaller output voltage steps that mitigate motor issues due to long power cables between the inverter and the motor. These issues can include, for example, motor shaft bearing currents, and excessive voltage rates. In addition, the cleaner output waveform provides an effective switching frequency twice that of the actual switching frequency. Should an output filter be required, the components will be smaller and less costly than for an equivalent rated two level inverter. Most often the three-level inverter has been used for higher voltages. Because the IGBTs are only subjected to half of the bus voltage, lower voltage switches can be used.
FIG. 2A shows a conventional three-phase three-level inverter using four IGBTs plus two diodes on each phase leg. Outputs include U, V, and W phases, which can be connected for motor drive.
FIG. 2B shows a conventional soft-switched three-level inverter, with the snubber circuit highlighted.
FIG. 2C shows one phase leg of the inverter of FIG. 2A. IGBTs Q1 and Q2 are activated to connect to positive voltage Vp; Q2 and Q3 are activated to connect to intermediate voltage Vo; and Q3 and Q4 are activated to connect to negative voltage Vn.
FIG. 2D shows the phase leg output voltage, and FIG. 2E shows the phase-to-phase output voltage, for one example of PWM operation of the inverter of FIG. 2A.
Further background can be found in the following publications, all of which are hereby incorporated by reference: Applikationshandbuch IGBT-und MOSFET-Leistungsmodule (ed. P. Martin 1998), Section 1.2.3 Qualitatives Schaltverhalten von MOSFET und IGBT beim harten Schalten (PDF); Nabae et al., “A New Neutral-Point-Clamped PWM Inverter,” 17 IEEE Trans'ns on Industry App'ns 518-523 (1981); Schweizer et al., “High efficiency drive system with 3-level T-type inverter,” Proc. 14th European Conference on Power Electronics and Applications (EPE 2011) at 1-10; Gekeler, “Soft switching three level inverter with passive snubber circuit (S3L inverter),” in Proceedings of the 2011-14th European Conference on Power Electronics and Applications (EPE 2011) 1-10; Gekeler, “Weich schaltender 3-Stufen-Pulswechselrichter mit verlustfreiem Entlastungsnetzwerk,” in International ETG Congress 2011 (ETG Technical Report 130 Part B) at 264-270; U.S. Pat. No. 8,462,524; U.S. Pat. No. 6,838,925; Erdman et al., “A 2.3-MW Medium-Voltage, Three-Level Wind Energy Inverter Applying a Unique Bus Structure and 4.5-kV Si/SiC Hybrid Isolated Power Modules,” http://www.nrel.gov/docs/fy15osti/63189.pdf (not prior art); the Powerex application note found at http://www.pwrx.com/pwrx/app/TLI%20Series%20 Application%20Note.pdf; and Alepuz et al., “Interfacing Renewable Energy Sources to the Utility Grid Using a Three-Level Inverter,” https://www.infona.pl/resource/bwmetal. element.ieee-art-000001705641.